The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, as fin-like field effect transistor (FinFET) technologies progress towards sub-micron feature sizes, decreasing fin pitches and increasing fin heights are placing significant constraints on multi-layer interconnect (MLI) features used to facilitate operation of FinFET devices. For example, interconnect structures currently provided in advanced technology node MLI features exhibit higher than desirable resistance and poor electromigration performance. Accordingly, although existing interconnect structures and corresponding formation techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.